The SMV512K32 is a high performance asynchronous CMOS SRAM organized as 524,288 words by
32 bits. It is pin selectable between two modes: master or slave. The master device selection
provides user defined autonomous EDAC scrubbing options. The slave device selection employs a scrub
on demand feature that can be initiated by a master device. Three read cycles and four write cycles
(described below) are available depending on the user needs.
- 20-ns Read, 13.8-ns Write Through Maximum Access Time
- Functionally Compatible With Commercial
512K x 32 SRAM Devices - Built-In EDAC (Error Detection and Correction) to Mitigate Soft Errors
- Built-In Scrub Engine for Autonomous Correction
- CMOS Compatible Input and Output Level, Three State Bidirectional
Data Bus - 3.3 ±0.3-V I/O, 1.8 ±0.15-V CORE
- Radiation Performance(1)
- Uses Both Substrate Engineering and Radiation Hardened by Design (HBD)(2)
- TID Immunity > 3e5 rad (Si)
- SER < 5e-17 Upsets/Bit-Day (Core Using EDAC and Scrub)(3)
- Latch up immunity > LET = 110 MeV (T = 398K)