DRA724JGABCRQ1

760-FCBGA (23x23) 1 GHz Arm Cortex-A15 SoC processor with graphics and DSP for automotive infotainment & cluster

Manufacturer：

Luminary Micro/Texas Instruments

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Manufacturer NO：

DRA724JGABCRQ1

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Product SN：

10447-DRA724JGABCRQ1

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Package/Case：

760-BFBGA, FCBGA

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Manufacturer Lead Time：

-

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Datasheet:

DRA724JGABCRQ1 Datasheet PDF

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Detailed Descripition：

Multimedia

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Product Application Field：None

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Environmental & Export Classifications

RoHS Status

ROHS3 Compliant

Moisture Sensitivity Level (MSL)

3 (168 Hours)

Documents & Media

Datasheets PDF DRA724JGABCRQ1 Datasheet PDF

Product Description

DRA72x ("Jacinto™ 6 Eco") infotainment applications processors are developed on the same architecture as Jacinto 6 devices to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatible across the family, allowing Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 and Jacinto 6 Eco devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution.

Programmability is provided by a single-core Arm^® Cortex^®-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm^® processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm^®, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment is available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100 standard.

Architecture designed for infotainment applications
Video, image, and graphics processing support
- Full-HD video (1920 × 1080p, 60 fps)
- Multiple video inputs and video outputs
- 2D and 3D graphics
Arm^® Cortex^®-A15 microprocessor subsystem
C66x floating-point VLIW DSP cores
- Fully object-code compatible with C67x and C64x+
- Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
Up to 512KB of on-chip L3 RAM
Level 3 (L3) and level 4 (L4) interconnects
DDR3/DDR3L External Memory Interface (EMIF) module
- Supports up to DDR3-1333 (667 MHz)
- Up to 2GB across single chip select
Dual Arm^® Cortex^®-M4 Image Processing Units (IPU)
IVA-HD subsystem
Display subsystem
- Display controller with DMA engine and up to three pipelines
- HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
2D-graphics accelerator (BB2D) subsystem
- Vivante^® GC320 core
Video Processing Engine (VPE)
Single-core PowerVR™ SGX544 3D GPU
One Video Input Port (VIP) module
- Support for up to four multiplexed input ports
General-Purpose Memory Controller (GPMC)
Enhanced Direct Memory Access (EDMA) controller
2-Port Gigabit Ethernet switch
- Up to two external ports
Sixteen 32-bit general-purpose timers
32-bit MPU watchdog timer
Six high speed Inter-Integrated Circuit (I²C™) ports
HDQ/1-Wire^® interface
Ten configurable UART/IrDA/CIR modules
Four Multichannel Serial Peripheral Interfaces (McSPI)
Quad Serial Peripheral Interface (QSPI)
Media Local Bus subsystem (MLBSS)
Real-Time Clock subsystem (RTCSS)
SATA interface
Eight Multichannel Audio Serial Port (McASP) modules
SuperSpeed USB 3.0 dual-role device
High Speed USB 2.0 dual-role device
High Speed USB 2.0 on-the-go
Four MultiMedia Card/Secure Digital^®/Secure Digital Input Output interfaces (MMC™/SD^®/SDIO)
PCI-Express^® (PCIe^®) revision 3.0 subsystems with two 5-Gbps lanes
- One 2-lane Gen2-compliant port
- or two 1-lane Gen2-compliant ports
Dual Controller Area Network (DCAN) modules
- CAN 2.0B Protocol
MIPI^® Camera Serial Interface 2 (CSI-2)
Up to 215 General-Purpose I/O (GPIO) pins
Device security features
- Hardware crypto accelerators and DMA
- Firewalls
- JTAG lock
- Secure keys
- Secure ROM and Boot
- Customer programmable keys (Silicon Revision 2.1)
Power, reset, and clock management
On-chip debug with CTools technology
28-nm CMOS technology
23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)