DRA783BRJABFQ1

SoC processor w/ 2x 750 MHz C66x DSP and 2 dual Arm Cortex-M4 for audio amplifier

Manufacturer：

Luminary Micro/Texas Instruments

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Manufacturer NO：

DRA783BRJABFQ1

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Product SN：

10442-DRA783BRJABFQ1

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Package/Case：

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Manufacturer Lead Time：

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Datasheet:

DRA783BRJABFQ1 Datasheet PDF

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Detailed Descripition：

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Product Description

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8 mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

Architecture designed for infotainment applications
Up to 2 C66x floating-point VLIW DSP
- Fully object-code compatible with C67x and C64x+
- Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
Up to 512kB of on-chip L3 RAM
Level 3 (L3) and Level 4 (L4) interconnects
Memory Interface (EMIF) module
- Supports DDR3/DDR3L up to DDR-1066
- Supports DDR2 up to DDR-800
- Up to 2GB supported
Dual Arm^® Cortex^®-M4 (IPU)
Vision accelerationPac
- Embedded Vision Engine (EVE)
Display subsystem
- Display controller with DMA engine
- CVIDEO / SD-DAC TV analog composite output
On-chip temperature sensor that is capable of generating temperature alerts
General-Purpose Memory Controller (GPMC)
Enhanced Direct Memory Access (EDMA) controller
3-port (2 external) Gigabit Ethernet (GMAC) switch
Controller Area Network (DCAN) module
- CAN 2.0B protocol
Modular Controller Area Network (MCAN) module
- CAN 2.0B protocol
Eight 32-bit general-purpose timers
Three configurable UART modules
Four Multichannel Serial Peripheral Interfaces (McSPI)
Quad SPI interface
Two Inter-Integrated Circuit (I²C™) ports
Three Multichannel Audio Serial Port (McASP) modules
Secure Digital Input Output Interface (SDIO)
Up to 126 General-Purpose I/O (GPIO) pins
Power, reset, and clock management
On-chip debug with CTools technology
Automotive AEC-Q100 qualified
15 × 15 mm, 0.65-mm pitch, 367-pin PBGA (ABF)
Five instances of Real-Time Interrupt (RTI) modules that can be used as watch dog timers
8-channel 10-bit ADC
PWMSS
Video and image processing support
- Full-HD video (1920 × 1080p, 60 fps)
- Video input and video output
- GPIOs when not used for video
Video Input Port (VIP) module
- Support for up to 4 multiplexed input ports