V62/13608-01XE

Enhanced Product 4-A/8-A single-channel gate driver with 5-V UVLO in SON package

Manufacturer：

Luminary Micro/Texas Instruments

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Manufacturer NO：

V62/13608-01XE

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Product SN：

10506-V62/13608-01XE

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Package/Case：

WSON (DRS)-6

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Manufacturer Lead Time：

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Datasheet:

V62/13608-01XE Datasheet PDF

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Detailed Descripition：

Hysteretic Logic

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Product Application Field：None

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Customer Reference

Quantity

Product price

Qty

Unit Price

Ext Price

1000

$1.625

$1625

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Documents & Media

Datasheets PDF V62/13608-01XE Datasheet PDF

Product Description

The UCC27512 single-channel, high-speed, low-side gate driver device is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC27512 is capable of sourcing and sinking high, peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay typically 13 ns.

The UCC27512 provides 4-A source, 8-A sink (asymmetrical drive) peak-drive current capability. Strong sink capability in asymmetrical drive boosts immunity against parasitic, Miller turn-on effect.

UCC27512 is designed to operate over a wide VDD range of 4.5 V to 18 V and wide temperature range of 55°C to 125°C. Internal Under Voltage Lockout (UVLO) circuitry on VDD pin holds output low outside VDD operating range. The capability to operate at low voltage levels such as below 5 V, along with best in class switching characteristics, is especially suited for driving emerging wide band-gap power switching devices such as GaN power semiconductor devices.

Low-Cost, Gate-Driver Device Offering Superior Replacement
of NPN and PNP Discrete Solutions
4-A Peak Source and 8-A Peak Sink Asymmetrical Drive
Strong Sink Current Offers Enhanced Immunity Against Miller Turn On
Fast Propagation Delays (13-ns typical)
Fast Rise and Fall Times (9-ns and 7-ns typical)
4.5-V to 18-V Single Supply Range
Outputs Held Low During VDD UVLO (ensures glitch free operation at
power-up and power-down)
TTL and CMOS Compatible Input Logic Threshold,
(independent of supply voltage)
Hysteretic Logic Thresholds for High Noise Immunity
Dual Input Design (choice of an inverting (IN- pin) or non-inverting
(IN+ pin) driver configuration)
- Unused Input Pin can be Used for Enable or Disable Function
Output Held Low when Input Pins are Floating
Input Pin Absolute Maximum Voltage Levels Not Restricted by VDD Pin
Bias Supply Voltage
6-Pin DRS (3mm × 3 mm WSON with exposed thermal pad) Package